1/7 preliminary data february 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. STD40NF03L n-channel 30v - 0.0095 w - 40a dpak low gate charge stripfet?ii power mosfet n typical r ds (on) = 0.0095 w n typical q g = 35 nc @ 10v n optimal r ds(on) x qg trade-off n conduction losses reduced n switching losses reduced description this application specific power mosfet is the third genaration of stmicroelectronis unique "single feature size?" strip-based process. the resulting transistor shows the best trade-off between on-resistance and gate charge. when used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. this is extremely important for motherboards where fast switching and high efficiency are of paramount importance. applications n specifically designed and optimised for high efficiency cpu core dc/dc converters type v dss r ds(on) i d STD40NF03L 30 v <0.012 w 40 a 1 3 dpak to-252 (suffix t4) add suffix t4 for ordering in tape & reel absolute maximum ratings ( ) current limited by the package ( ) pulse width limited by safe operating area. symbol parameter value unit v ds drain-source voltage (v gs = 0) 30 v v dgr drain-gate voltage (r gs = 20 k w ) 30 v v gs gate- source voltage 18 v i d ( ) drain current (continuous) at t c = 25c 20 a i d drain current (continuous) at t c = 100c 20 a i dm ( ) drain current (pulsed) 80 a p tot total dissipation at t c = 25c 55 w derating factor 0.37 w/c t stg storage temperature -65 to 175 c t j max. operating junction temperature 175 c internal schematic diagram
STD40NF03L 2/7 thermal data electrical characteristics (t case = 25 c unless otherwise specified) off on (* ) dynamic rthj-case rthj-amb t l thermal resistance junction-case thermal resistance junction-ambient maximum lead temperature for soldering purpose max max typ 2.73 62.5 300 c/w c/w c symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a, v gs = 0 30 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating v ds = max rating t c = 125c 1 10 a a i gss gate-body leakage current (v ds = 0) v gs = 18v 100 na symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds = v gs i d = 250 a 1v r ds(on) static drain-source on resistance v gs = 10 v i d = 20 a v gs = 5 v i d = 20 a 0.0095 0.019 0.012 0.022 w w symbol parameter test conditions min. typ. max. unit g fs (*) forward transconductance v ds >i d(on) xr ds(on)max i d =20 a 40 s c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds = 25v, f = 1 mhz, v gs = 0 1470 490 110 pf pf pf
3/7 STD40NF03L switching on switching off source drain diode (*) pulsed: pulse duration = 300 s, duty cycle 1.5 %. ( ) pulse width limited by safe operating area. symbol parameter test conditions min. typ. max. unit t d(on) t r turn-on delay time rise time v dd = 15 v i d = 20 a r g = 4.7 w v gs = 4.5 v (resistive load, figure 3) 20 170 ns ns q g q gs q gd total gate charge gate-source charge gate-drain charge v dd =24 v i d =40 a v gs =10v 35 5 10 45 nc nc nc symbol parameter test conditions min. typ. max. unit t d(off) t f turn-off delay time fall time v dd = 15 v i d = 20 a r g = 4.7 w, v gs = 4.5 v (resistive load, figure 3) 40 60 ns ns symbol parameter test conditions min. typ. max. unit i sd i sdm ( ) source-drain current source-drain current (pulsed) 20 80 a a v sd (*) forward on voltage i sd = 20 a v gs = 0 1.5 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 20 a di/dt = 100a/s v dd = 15 v t j = 150c (see test circuit, figure 5) 70 105 2.4 ns nc a electrical characteristics (continued)
STD40NF03L 4/7 fig. 1: unclamped inductive load test circuit fig. 1: unclamped inductive load test circuit fig. 2: unclamped inductive waveform fig. 3: switching times test circuits for resistive load fig. 4: gate charge test circuit fig. 5: test circuit for inductive load switching and diode recovery times
5/7 STD40NF03L dim. mm inch min. typ. max. min. typ. max. a 2.2 2.4 0.086 0.094 a1 0.9 1.1 0.035 0.043 a2 0.03 0.23 0.001 0.009 b 0.64 0.9 0.025 0.035 b2 5.2 5.4 0.204 0.212 c 0.45 0.6 0.017 0.023 c2 0.48 0.6 0.019 0.023 d 6 6.2 0.236 0.244 e 6.4 6.6 0.252 0.260 g 4.4 4.6 0.173 0.181 h 9.35 10.1 0.368 0.397 l2 0.8 0.031 l4 0.6 1 0.023 0.039 == d l2 l4 1 3 == b e == b2 g 2 a c2 c h a1 detail "a" a2 detail "a" to-252 (dpak) mechanical data 0068772-b
STD40NF03L 6/7
7/7 STD40NF03L information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics a 2002 stmicroelectronics - all rights reserved all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http://www.st.com
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